In the fabrication of integrated circuits using metal oxide semiconductor (MOS) techniques, gate oxide layers are becoming increasingly thinner in order to achieve further increases in transistor performance. For a given set of terminal voltages, the drain current of an MOS transistor is inversely proportional to the thickness of the gate oxide. A "thin gate transistor" may have a gate oxide layer which is less than 300 .ANG. thick. Decreasing the length of transistor channels also enhances the performance of an integrated circuitry.
A decrease in the thickness of the gates of an integrated circuit renders the circuit more susceptible to gate-aided junction breakdown. Gate-aided junction breakdown will cause incorrect voltage levels in a logic circuit, high power dissipation, and possibly irreversible damage to the affected transistors.
Many non-volatile devices, including EPROMs, EEPROMs, PLDs and FPGAs, require operation at high voltages without breakdown. For example, a high voltage may be used in a write or erase operation. Circuits which include protection against breakdown at high voltages are known. Such circuits are described in U.S. Pat. Nos. 4,161,663 to Martinez, 4,689,504 to Raghunathan et al., 4,845,381 to Cuevas, and 5,054,001 to Guillot. While prior art circuits work well as designed, there are certain disadvantages. For example, some circuits require not only the conventional supply voltage (V.sub.cc) and the high operating voltage (V.sub.pp), but also require an intermediate voltage (V.sub.1 and V.sub.2). Another disadvantage is that some of the known circuits are limited to switching between V.sub.pp and ground at an output node or switching between V.sub.pp and V.sub.cc at the output node. Circuits that allow selecting between V.sub.pp and ground or between V.sub.cc and ground are typically complex. The complexity often reduces the speed of the circuit.
It is an object of the present invention to provide a high voltage circuit that permits use of high speed, thin gate transistors without rendering the circuit susceptible to gate-aided junction breakdown and without complexity.